This invention relates to an etching process for manufacturing a semiconductor device, and more particularly to a method for accurately detecting the etching end point or monitoring the etching depth with high precision and an etching apparatus using the above method.
When a semiconductor device is manufactured, the etching process is effected in various steps such as patterning a conductive layer used as wirings and electrodes, forming contact holes and through holes, and forming shallow trenches for device isolation. In the above various etching steps, conventionally, the etching end point is detected by a measuring or predicting method using, for example, (a) visual observation by the operator, (b) interrupting the progress of the etching process by using a stopper layer formed of a material having a high selective etching ratio with respect to a material to be etched, (c) predicting the etching depth based on the etching rate of a sample previously processed and controlling the etching depth according to the etching time, (d) predicting the etching depth by measuring the amount of a gas emitted at the time of etching, and (e) measuring the etching depth by use of the interference of the laser beam due to the optical path difference between the incident light and the reflected light.
In recent years, for highly integrated electric circuits, for example, DRAMs, STI (shallow trench isolation) structures and DT (deep trench) structures are employed widely. In a DRAM with STI structure, a shallow trench is formed on the semiconductor surface and an insulating material fills up the trench to attain electrical isolation between devices. In a DRAM with DT structure, a deep trench is formed on the main surface of the semiconductor substrate and capacitor electrodes are embedded in the trench to attain a large capacitance without increasing the chip occupancy area. In order to form the STI structure or DT structure, it is required to use a technique for forming a fine trench with high precision by the etching process.
However, if any one of the above etching end point detecting methods (a) to (e) is used, it is difficult to detect an etching end point with such sufficiently high precision that is required for fabrication of a 256 Mb DRAM and for an electrical circuit of even larger integration, a large-scale measuring equipment is required and the cost of the etching apparatus is raised. For example, with the method (a), it is difficult to accurately determine the etching depth and it is almost impossible to determine the etching end point, particularly, when the etching process with a high aspect ratio is required as in the DT structure. For trench formation in a semiconductor substrate made of a single material, the method (b) cannot be used. Further, since the methods (c) and (d) are based on prediction or indirect measurement, they tend to be influenced by a fluctuation in the manufacturing process and a required high precision cannot be attained. Further, with the method (e), since the depth is directly measured, the precision is high but it is necessary to mount a measuring device using a laser beam on the etching apparatus, thereby making the apparatus expensive.
In order to solve the above problems, an electrolytic etching techniques utilizing selective formation of an anode oxide film on an n-type impurity layer and resultant sharp drop of etching current to detect completion of etching of p-type layer is disclosed in U.S. Pat. No. 5,173,149. Further, in U.S. Pat. No. 4,358,338, a physical etching technique for detecting the etching end-point by monitoring the etching current from plasma through a target being etched is disclosed. Further, in Jpn. Pat. Appln. KOKAI Publication No. 60-167332, a RIE etching technique is disclosed in which, after forming an impurity layer extending to the same depth as a groove to be etched and, attaching a pair of measuring probes to opposite sides of the groove, the etching process is stopped when the electrical resistance between them abruptly increases.
However, the technique disclosed in U.S. Pat. No. 5,173,149 is applied to the wet etching process and cannot be applied to the anisotropic etching process such as an RIE (Reactive Ion Etching) process required for forming the STI structure or DT structure. Further, in the technique disclosed in U.S. Pat. No. 4,358,338, the etching end-point is detected by measuring a current flowing from etching plasma through the object being etched. In order to apply the method for an etching process of small and deep trenches, in which total etching area amounts to only a small fraction of total surface area of the object, the current level becomes low, thereby making it difficult to detect the etching end point. Further, in the technique disclosed in Jpn. Pat. Appln. KOKAI Publication No. 60-167332, it is necessary to apply a pair of measuring probes to opposite sides of the groove and the technique cannot be applied to the STI structure and DT structure having hole-like trenches, because a large number of current paths remains even after completion of the etching.